主要经历（教育及工作经历）：

1995年02月-1998年02月 上海交通大学电院博士研究生

1998年02月-2000年06月 浙江大学信电系博士后

2000年06月-2003年06月 复旦大学专用集成电路与系统国家重点实验室博士后

2007年06月 比利时微电子研究中心IMEC培训学习

2003年06月-至今 复旦大学微电子学院教授

研究方向:

1）可编程芯片设计及其测试方法研究

2）基于FPGA的神经网络加速器设计方法研究

3）基于SoC FPGA的深度学习研发平台设计

4）嵌入式可编程 IP 核及其软硬件设计方法研究

主讲课程：

“信号与通信系统 ” （本科生）

“集成电路设计基础”（ 科硕研究生）

“VLSI系统设计导论”（工硕研究生）

“集成电路设计透视” （书院课程)

荣誉和奖励：

上海市巾帼创新奖，2007

适用于数据通路应用的可编程逻辑器件及其软件系，获高等学校科技进步二等奖（2），颁证（奖）单位：中华人民共和国教育部，2007

年度微电子研究院先进个人奖，2007

年度学院奖教金二等奖，2008

近期发表论文：

[1] Xiong, Wei，Lai, Jinme，An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique，Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI，2022，275-280

[2] Qingliang Liu, Jinmei Lai, Jiabao Gao. An Efficient Channel-Aware Sparse Binarized Neural Networks inference Accelerator, IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(3): 1637-1641.

[3] Jiabao Gao, Qingliang Liu and Jinmei Lai. An Approach of Binary Neural Network Energy-Efficient Implementation, Electronics, 2021,10(15), 1380. (IF为2.397  )

[4] Jiabao Gao, Yuchen Yaoi, and Jinmei Lai. FCA-BNN Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA, IEICE transaction on information and system, 2021, E104.D(8): 1367-1377.

[5] Qingliang Liu, Jiabao Gao, Jinmei Lai. TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021: 1-5.

[6] Zhengjie Li, Jiabao Gao, Jinmei Lai. HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure, IEICE Transactions on Information and Systems, 2021, E104.D(10): 1724-1733.

[7] Qingliang Liu, Jinmei Lai, Stochastic Loss Function, AAAI Conference on Artificial Intelligence (AAAI2020)

[8] Chengyu Hu, Peng Lu, Meng Yang, Jian Wang, Jinmei Lai, A SA-based parallel method for FPGA placement, IEICE Electronics Express, 2018-12-25，Volume 15, Issue 24, Pages 20180943.

[9] Jiabao. Gao, Jian Wang, M. T. Arafin, Jinmei Lai. FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs, 2020 IEEE 33rd International System-on-Chip Conference (SOCC), 2020: 207-212.

[10] Lu Z Y, Liu J F, Pang Y B , et al. A Low-delay Configurable Register for FPGA[C]// 2019 IEEE 13th International Conference on ASIC (ASICON). IEEE, 2019.

[11] Yunbing Pang, Jiqing Xu, Yufan Zhang, Xinxuan Tao*, Jian Wang, Meng Yang, Jinmei Lai*，Research on Circuit-Level Design of High Performance and Low Power FPGA Interconnect Circuits in 28nm Process，ICSICT 2018，2018 IEEE 14th International Conference on Solid-State and Integrated Circuit Technology, Oct.31-Nov. 3,2018,Qingdao,China

[12] Zhen Yang, Chuanzeng Liang, Jian Wang, and Jinmei Lai ,Testing Modern FPGA Local Interconnects Based On Repeatable Configuration Modules, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2016)

[13] Yuanlong Xiao, Jian Wang, and Jinmei Lai，A Universal Automatic On-Chip Measurement of FPGA's Internal Setup and Hold Times，IEICE Electronics Express, Publicized December 10, 2016

[14] Xu Hanyang，Lai Jinmei，A FPGA Prototype Design Emphasis on Low Power Technique，FPGA2014, Proceedings of the 2014 ACM/SIGDA International Symposium on Field Programmable Gate Array, Monterey California,USA

[15] Chun Zhu, Jian Wang, Jinmei Lai，A Novel Net-Partition-Based Multithread FPGA Routing Method，23rd international conference on field programmable logic and applications,FPL 2013 , Porto,Portugal,Sept.2-4,2013,oral

[16] Hanyang Xu, Jian Wang, and Jinmei Lai，Prototyping design of a flexible DSP block with pipeline structure for FPGA，IEICE Electronics Express,Publicized August 19, 2016

[17] Wen Yu，Jin-mei Lai，A Fully Digital DLLs Integrated in FPGAs，ICSICT 2008，The 9th International Conference on Solid-State and Integrated-Circuit Technology，October 20-23, 2008,Beijing Jingyi Hotel, Beijing, China