研究方向:
(1)先进半导体器件的设计、工艺和模型;(2)基于人工智能的集成电路设计自动化(EDA)技术
教育背景:
2006年7月-2011年9月 美国宾夕法尼亚大学,博士
2002年9月-2006年6月 南京大学,学士
学术经历:
2020年1月-至今 复旦大学教授
2016年10月-2019年12月 高通公司 主任研究员
2011年10月-2016年9月 英特尔公司 资深研究员
荣誉获奖:
国家级高层次青年引进人才 2019
上海市高层次引进人才 2020
高通超级星和高通之星奖(共6次)2016-2019
英特尔逻辑技术发展奖(共2次)2011-2016
学术成果:
近期代表性论文:
(1) Baowei Yuan; Zhibo Chen; Yingxin Chen; Chengjie Tang; Weiao Chen; Zengguang Cheng; Chunsong Zhao; Zhaozhao Hou; Qiang Zhang; Weizhuo Gan; Jiacheng Gao; Jiale Wang; Jeffrey Xu; Guangxi Hu; Zhenhua Wu; Kun Luo; Mingyan Luo; Yuanbo Zhang; Zengxing Zhang; Shisheng Xiong; Chunxiao Cong; Wenzhong Bao; Shunli Ma; Jing Wan; Peng Zhou; Ye Lu ; High drain field impact ionization transistors as ideal switches, Nature Communications, 2024, 15(1): 1-8
(2) Zhibo Chen; Weiao Chen; Baowei Yuan; Yingxin Chen; Chengjie Tang; Weizhuo Gan; Chunsong Zhao; Zhaozhao Hou; Qiang Zhang; Jiachen Gao; Jiale Wang; Jeffrey Xu; Shisheng Xiong; Jing Wan; Ye Lu ; An Al-Drain Silicon Transistor With Ultra-steep Subthreshold Slope and Low Operating Voltage, IEEE Electron Device Letters (EDL), 2025, 46(3): 496-499
(3) Jinxin Zhang; Jiarui Bao; Zhangcheng Huang; Xuan Zeng; Ye Lu ; Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning, 60th IEEE Design AutomationConference(DAC), San Francisco, USA, 2023-7-9至2023-7-13
(4) Jiarui Bao; Jinxin Zhang; Zhangcheng Huang; Zhaori Bi; Xingwei Feng; Xuan Zeng; Ye Lu ; Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024, 43(12): 4398-4411
(5) Guodong Qi; Weizhuo Gan; Lijun Xu; Jiangtao Liu; Qihang Yang; Xiaona Zhu; Jiuren Zhou; Xinyu Ma; Guangxi Hu; Tao Chen; Shaofeng Yu; Zhenhua Wu; Huaxiang Yin; Ye Lu ; The Device and Circuit Level Benchmark of Si-based Cold Source FETs for Future Logic Technology, IEEETransactions on Electron Devices (TED), 2022, 69(6): 3483-3489
(6) Q. Yang; G. Qi; W. Gan; Z. Wu; H. Yin; T. Chen; G. Hu; J. Wan; S. Yu; Ye Lu ; Transistor Compact Model Based on Multi-gradient Neural Network and Its Application in SPICE Circuit Simulations for Gate All-Around Si Cold Source FETs, IEEE Transactions on Electron Devices (TED), 2021, 68(9): 4181-4188
(7) Yunlin Liu; Xiaohe Huang; Kun Luo; Zhenhua Wu; Yan Liu; Chunsen Liu; Guangxi Hu; Peng Zhou; Ye Lu ; A Quantum Corrected Compact Model of Experimentally Fabricated GAA 2D MBCFETs, IEEETransactions on Electron Devices (TED), 2023, 70(3): 891-898
(8) P. Kushwaha; H. Agarwal; Y. Lin; A. Dasgupta; M. Kao; Y. Lu*; Y. Yue; X. Chen; J. Wang; W.Sy; F.Yang; P. C. Chidambaram; S. Salahuddin; Chenming Hu ; Characterization and Modeling of Flicker Noise in FinFETs at Advanced Technology Node, IEEE Electron Device Letters (EDL), 2019, 40(6):985-988
(9) Xiaona Zhu; Rongzheng Ding; Ouwen Tao; Yage Zhao; Peishun Tang; David Wei Zhang; Ye Lu*; Shaofeng Yu ; A combined N/PFET Complementary FET based design and technology framework for CMOS
applications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023, 42(12): 4999-5006
(10) S. Ramey; Y. Lu; I. Meric; S. Mudanai; S. Novak; C. Prasad; J. Hicks ; Aging model challenges in deeply scaled tri-gate technologies, 2015 IEEE International Integrated ReliabilityWorkshop (IIRW), South Lake Tahoe, CA, USA, 2015-10-11至2015-10-15
代表性专利:
(1) 陆叶; 杨启航; 齐国栋 ; 基于多梯度神经网络的半导体器件特性建模方法和系统, 2022-4-12, 中国, ZL 2020 1 1393933.3
(2) Y.Lu; Y.Yue; C.Chen; B.Yang; L.Ge; K.Liao ; Self-aligned contact (SAC) on gate for improving metal oxide semiconductor (MOS) varactor quality factor, 2019-6-25, 美国, US 10 , 333 ,007 B2
(3) Y.Lu; C.Song; H.Cheng ; STACKED RESISTOR-CAPACITOR DELAY CELL, 2018-8-28, 美国, US 10,629,590 B2
(4) Y.Lu; H.Yang ; GATE CUT LAST PROCESSING WITH SELF-ALIGNED SPACER, 2019-2-15, 美国, US 2020/0035674 A1
(5) Y.Lu; J.Bao; B.Yang ; MULTIPLE LAYER CYLINDRICAL CAPACITOR, 2018-6-11, 美国, US 2019/0378657 A1
其他:
每年计划招收博士/硕士共 3 - 6 名,欢迎有志于在人工智能、集成电路芯片方向发展,并有微电子、物理、集成电路、材料等学科背景的同学报考。课题组有充足资源,并与产业界有良好合作,已经毕业学生均获得中直机关、行业领头企业、及创业的机会。