个人简介：

复旦大学集成电路与微纳电子创新学院教授，IEEE高级会员，2025年入选国家人才项目。主要研究方向为集成电路设计与计算机辅助设计。已在本领域的权威国际期刊和会议IEEE Trans. on CAD、IEEE Trans. on CAS、DAC、ICCAD、DATE等上发表论文近百篇。多次承担/参与国家科技重大专项、重点研发、自然科学基金等项目。多次担任本领域顶会DAC、ASPDAC、FPL等TPC member，以及国际学术期刊IEEE Trans. on CAD、IEEE Trans. on VLSI、ACM Trans. on DAES等审稿人。

研究方向:

AI-based EDA

AI加速算法及AI加速器设计优化

混合信号系统建模与优化

统计数据分析

芯粒集成系统自动化设计

教育及学术经历：

2022年-至今      复旦大学集成电路与微纳电子创新学院教授

2016年-2021年  复旦大学微电子学院副教授

2012年-2013年  美国卡内基梅隆大学电子计算机工程系访问学者

2008年-2015年  复旦大学微电子学院讲师

2007年               复旦大学微电子学系博士

代表性论文：

[1]   Chuyi Dai, Chen Ye1, Zeyu Li, Jun Tao, Wei Zhang, Grace Li Zhang and Xin Li, “GCPT: Gradient-aware Clustering Method for Efficient Post-Training Quantization in Large Neural Networks,” DATE 2026.

[2]   Jiaming Liu, Xuan Huang, Zhijian Hao, Ruoxi Zhu, Qi Zheng, Shuocheng Wang, Shushi Chen, Chang Liu, Leilei Huang, Jun Tao and Yibo Fan, “MAS-ISP: A Proxy-Free Online Hyperparameter Optimization Framework for ISP Hardware System,” DAC, 2025.

[3]   B. Jiao, H. Zhu, Y. Zeng, Y. Li, J. Liao, S. Jia, Z. Chen, M. Tian, J. Zhu, D. Wen, Y. Wang, Y. Wang, J. Xu, F. Wang, J. Tao, C. Chen, Q. Liu, M. Liu, “SHINSAI: A 586mm2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory,” International Solid-State Circuits Conference (ISSCC), 2025.

[4]  Kun Wu, Yuncheng Liu, Hui Gao, Jun Tao, Wei Xiong and Xin Li, “Efficient Design Optimization for Diffractive Deep Neural Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 44, iss. 3, pp. 1199-1203, March 2025.

[5]  Nanning Guo, Sihui Chen (共同一作), Jun Tao, Yang Liu, Jiayu Wan, and Xin Li, “Semi-supervised learning for explainable few-shot battery lifetime prediction,” Joule, vol. 8, iss. 6, pp. 1820-1836, 2024. (影响因子36)

[6]  Bo Jiao, Lei Xu, Xinyu Yu, Haitao Yang, Haozhe Zhu, Yu Wang, Jundong Zhu, Dexin Wen, Lingli Wang, Jun Tao, Chixiao Chen, Yinhe Han, Qi Liu, Ninghui Sun, Ming Liu, “FPIA: Communication-Aware Multi-Chiplet Integration with Field-Programmable Interconnect Fabric on Reusable Silicon Interposer,” IEEE Transactions on Circuits and Systems I: Regular Papers (IEEE TCAS-I), vol. 71, iss. 9, pp. 4156-4168, September 2024.

[7]  Jiaming Liu, Zihao Liu, Xuan Huang, Ruoxi Zhu, Qi Zheng, Zhijian Hao, Tao Liu, Jun Tao, Yibo Fan, “Auto-ISP: an efficient real-time automatic hyperparameter optimization framework for ISP hardware system,” DAC, 2024.

[8]  Nanlin Guo, Fulin Peng, Jiahe Shi, Fan Yang, Jun Tao, Xuan Zeng, “Yield optimization for analog circuits over multiple corners via bayesian neural networks: enhancing circuit reliability under environmental variation,” ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), vol. 29, iss. 115, article no. 12, November 2023.

[9] Kun Wu, Nanlin Guo, Fei Li, Nengyong Zhu, Jun Tao and Xin Li, “Efficient statistical parameter extraction for modeling MOSFET mismatch,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 5, pp. 1618-1622, 2023.

[10] Zhengqi Gao, Fa Wang, Jun Tao, Yangfeng Su, Xuan Zeng, Xin Li, “Correlated bayesian model fusion: efficient high-dimensional performance modeling of analog/RF integrated circuits over multiple corners,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 2, pp. 360-370, February 2023.

[11] Kaixiang Zhu, Hao Zhou, Wai-Shing Luk, Jun Tao and Lingli Wang, “Iterative and verifiable retiming for FPGA performance optimization,” International Symposium of Electronic Design Automation (ISEDA), 2023

[12] Jun Tao, Handi Yu, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li, “Correlated rare failure analysis via asymptotic probability evaluation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 4, pp. 813-826, 2022.

[13] Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng and Xin Li, “Fast statistical analysis of rare failure events with truncated normal distribution in high-dimensional variation space,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 3, pp. 789-793, March, 2022.

[14] Fulin Peng, Handi Yu, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng and Xin Li, “Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 39, no. 12, pp. 4971-4984, Dec., 2020.

[15]  Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi Tahoori and Xiaoyang Zeng, “Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit,” Design Automation Conference (DAC), 2020.

[16] Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian zhou and Xuan Zeng, “Efficient performance trade-off modeling for analog circuit based on Bayesian neural network,” International Conference on Computer Aided Design (ICCAD), 2019.

[17]Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng and Xin Li, “Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.

[18] Jun Tao, Handi Yu, Yangfeng Su, Dian Zhou, Xuan Zeng and Xin Li, Correlated Rare Failure Analysis via Asymptotic Probability Evaluation, IEEE Design Automation Conference (DAC), 2017.

[19] Changhai Liao, Jun Tao, Handi Yu, Zhangwen Tang, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li, “Efficient hybrid performance modeling for analog circuits using hierarchical shrinkage priors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no. 12, pp. 2148-2152, 2016.

[20] Handi Yu, Jun Tao, Changhai Liao, Yangfeng Su, Dian Zhou, Xuan Zeng and Xin Li, “Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation,” IEEE International Conference on Computer Aided Design (ICCAD), 2016.